1. Field of Invention
The present invention relates generally to an upgradeable/downgradeable computer, and specifically to a computer having circuits capable of being driven by more than one model of central processing unit (CPU).
2. Description of the Related Art
As prices of CPUs decrease, the cost of a CPU as portion of the total cost of the whole system decreases, and as introduction of new types of central processors is becoming faster and faster (for example, within a span of only a few years, the Intel Corporation has introduced models 8086, 80286, 80386, 80486), it is now feasible to have a computer system that can be upgraded or downgraded by simply replacing processors. More specifically, it is desirable to have a computer system with circuitry (motherboard) that can accept different types of central processors without alteration.
FIG. 1 is a block diagram of a prior art system. As shown in FIG. 1, the system 10 is designed with two distinct sockets, the first socket 1' for 80486SX (80P23), and the second socket 2' for 80487SX (80P23N). In addition to the CPU clock signal (CLK) from the clock source 7', all other signals from/to data bus 100', address bus 101', and control bus 102' of the 80486SX, are tied to the corresponding signals of the 80487SX. The MP# signal of the 80487SX is tied high to allow the system 10 to function normally when the 80487SX is not present. When the 80487SX is inserted in the first socket 1', the MP# signal of the 80487SX drives the BOFF# signal and the FLUSH# signal of the 80486SX active, thus, tri-stating it. The 80487SX then takes charge of the buses 100', 101' and 102' and the system 10 works normally.